Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with buried gates (BG).
With buried gates, the integration degree of a cell transistor is increased in a method for fabricating a Dynamic Random Access Memory (DRAM) device using under 60 nm technology while securing proper operation characteristics. The buried gates are formed by forming trenches over a substrate and then filling the inside of each trench with a gate. By using such a method, the parasitic capacitance between bit lines and gates may be significantly decreased.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device with buried gates.
Referring to FIG. 1, the conventional semiconductor device with buried gates includes trenches 12 formed over a substrate 11, a gate insulation layer 13 formed on the surface of the trenches 12, a gate electrode 14 formed over the gate insulation layer 13 to fill a portion of each trench 12, and a sealing layer 15 formed over the gate electrode 14 to fill the remaining portion of the trench 12.
Here, since a buried gate forms the gate electrode 14 within each trench 12, resistivity characteristics and burial characteristics of the buried gate become significant. Therefore, the conventional technology may use a bi-layer structure where a titanium nitride layer (TiN) and a tungsten (W) layer are stacked to form the gate electrode 14.
As to the tungsten (CVD-W) layer, a barrier metal and a nucleation layer having relatively high resistivity compared with that of a bulk tungsten layer are used to prevent damages caused by fluorine. In having the relatively high resistivity, since the area of the bulk tungsten layer is decreased, proper resistance characteristics in accordance with a decreased linewidth of the bulk tungsten layer may be difficult to obtain. Further, since a barrier metal is used, there is a concern that the area of the tungsten layer is decreased.
To address such concerns, low-resistance titanium nitride (TiN) single layer formed by using a titanium tetrachloride (TiCl4) may be used as the gate electrode 14 of the buried gates. Since the titanium nitride (TiN) single layer formed by using a titanium tetrachloride (TiCl4) (that is, TiCl4—TiN) has excellent step coverage, it is often used as a line material of the gate electrode 14 filling the inside of the trenches 12.
A titanium nitride (TiN) layer deposited using a titanium tetrachloride (TiCl4) source includes chlorine (Cl) in the layer. Here, since chlorine is a material having a high electro-negativity and electron affinity in the Periodic Table, chlorine functions as an electron trapping sites even if the amount of chlorine within the titanium nitride (TiN) layer is minimal. Therefore, the concentration of chlorine is desired to be reduced to obtain a low resistance characteristic. Methods for decreasing the concentration of chlorine includes a method of depositing a thin film, such as several mono layers, through an Atomic Vapor Deposition (ALD) method or an ALD-like deposition method and performing a post-treatment to increase the efficiency of removing chlorine from a thin film, and a method of increasing a deposition temperature while using the same deposition method and thus increasing the speed of chlorine removal from the thin film. The foregoing methods, however, raises a concern that the step coverage is deteriorated when the deposition temperature is increased. Here, since the gate electrode 14 is disposed within trenches 12, the deterioration of the step coverage raises a concern that desired characteristics of the gate electrode 14 may deteriorate.